As advances continue to be made in the area of semiconductor memory devices, high capacity and low cost will be increasingly important. In particular, memory cell designs having a footprint no larger than 4F2 are increasingly desired to provide high density. FLASH memory has been a preferred technology for many years, but as devices continue to be scaled smaller, limits to FLASH memory devices are beginning to be reached. New technologies are being developed such as Magnetic RAM (MRAM), Resistive Change RAM (RRAM) and Phase Change RAM (PRAM). Unfortunately for these technologies, they will have to overcome an entrenched base of FLASH memory design wins in order to be adopted and succeed.
For high density storage applications, NAND FLASH has been the technology of choice because of its efficient memory cell (approximately 4F2). One tradeoff to achieving this efficient cell design is that many cells must be accessed in parallel for reading and writing. A typical NAND FLASH array segment is depicted in FIG. 1 showing an array of bit line chains. NAND FLASH uses a chain (i.e., that are connected in series) of floating-gate transistors. A single bit line chain is shown in FIG. 2. When all of the word lines are pulled high (above the VT of all of the transistors in the chain) a path through all of the transistors is completed and the bit line is pulled low. If a particular memory cell is programmed such that a charge is present on its floating gate, that cell will be “switched on” even without asserting the word-line connected to that gate (or by only raising that word-line to the VT of an erased bit). To read the array, a voltage is placed on all the word-lines other than to the cell to be accessed such that every transistor in the chain is switched on sufficiently to otherwise pass a current (i.e., word-lines are pulled up above the VT of a programmed bit regardless of the charge on their respective gates) and connect the bit-line through the chain to ground. If the particular memory cell to be accessed has a charge trapped on its gate, that transistor will also be switched on and the bit-line will be pulled low (to ground); otherwise, if the particular memory cell to be accessed has no charge trapped on its gate, that memory cell will be in the off state whereby it will interrupt the current path and the bit-line will remain high.
When bit-lines are being accessed as a part of an array (FIG. 1), because the word-lines are common to many chains, all the corresponding bit-lines are accessed at once and the many bits of data are accessed together. For writing the array, the given word-line is asserted with a higher programming voltage and each bit-line is either left floating or connected to a voltage (e.g., ground) depending upon the bit to be programmed. Because reading and writing are both operations that are performed on many bits simultaneously, large bit buffer registers are required to hold those bits to be programmed or to hold the read bits until they can be accessed in smaller groups (e.g., bytewise). To perform these and other operations on NAND FLASH (e.g., memory wearout management), a command based operation has been developed for these chips.
Many new technologies have been developed based on cross-point array designs (such as a diode matrix array) where a row and a column are selected and a resulting current passes through the targeted memory cell to write or read a data bit. Accessing these designs can be performed on a bitwise basis and these designs are truly random access parts. As a consequence, no large bit buffer registers are required. Other logic to support buffer-based operation and other functions to support NAND FLASH operation (such as “Read ID”, for example, are specified in the ONFI standard and implemented with additional logic is clear to those skilled in the art of NAND FLASH design) that are present in FLASH memory are not required in these new technologies. In so much as the bit buffer registers and other logic to support other FLASH functions can occupy a significant die area, cross-point array designs can be much more efficient than their NAND FLASH Memory predecessors.
What is needed is a random access, cross-point array memory device based on new PRAM, MRAM or RRAM technology that can be scaled beyond the scaling limits of FLASH, and for which there are existing designs for a potential quick design win. Furthermore, this needed memory device should be low cost to manufacture and should utilize existing manufacturing tools and techniques.